Electronic device and method for manufacturing the same

ABSTRACT

A manufacturing method of an electronic device comprises the steps of:  
     preparing a printed wiring board having a first region and a second region which differ from each other over one main surface thereof, a first electronic component having a plurality of first projection electrodes over one main surface thereof, and a second electronic component having a plurality of second projection electrodes which have a melting point higher than a melting point of the first projection electrodes over one main surface thereof;  
     mounting the first electronic component on the first region of one main surface of the printed wiring board by melting the plurality of first projection electrodes; and  
     mounting the second electronic component on the second region of one main surface of the printed wiring board by compression-bonding the second electronic component while heating in a state that an adhesive resin is interposed between the second region of one main surface of the printed wiring board and one main surface of the second electronic component  
     wherein the step of mounting the second electronic component is performed before the step of mounting the first electronic component.

TECHNICAL FIELD

[0001] The present invention relates to an electronic device and amanufacturing technique, and more particularly to a technique which iseffectively applicable to an electronic device adopting a flip-chippackaging technique.

BACKGROUND ART

[0002] As an electronic device, for example, an electronic devicereferred to as an MCM (Multi Chip Module) is known. The MCM mounts aplurality of semiconductor chips each incorporating an integratedcircuit therein on a printed wiring board on which a wiring pattern isformed and constitutes one compact function. In this MCM, to increasethe data transfer speed and to achieve the miniaturization of theelectronic device, the trend to adopt a flip-chip packaging techniquehas become active. The flip-chip packaging technique is a techniquewhich mounts semiconductor chips each arranging projection electrodes onone main surfaces thereof on a printed wiring board.

[0003] With respect to the flip-chip packaging technique, variousmounting methods have been proposed and put into practice. As typicalmounting methods among these mounting methods, for example, a methodwhich is referred to as CCB (Controlled Collapse Bonding) and a methodwhich is referred to as ACF (Anisotropic Conductive Film) mounting havebeen put into practice.

[0004] The CCB mounting method is a method which uses semiconductorchips having solder bumps made of a metal material of lead(Pb)-tin(Sn)composition, for example, as projection electrodes on one main surface,wherein the semiconductor chips are mounted on the printed wiring boardby melting the solder bumps. This CCB mounting method is, for example,described in “electronic material” [1996, April issue, pp.14-19]“published by Kogyo Chosakai”.

[0005] As electronic components which are mounted on the printed wiringboard by melting the solder bumps as in the case of the CCB mountingmethod, besides semiconductor chips (semiconductor chips for connectingsolder bumps), there have been known semiconductor devices of a BGA(Ball Grid Array) type which packages semiconductor chips, a CSP (ChipSize Package or Chip Scale Package) type and the like. This type ofsemiconductor device mounts semiconductor chips on one main surface sideof a printed wiring board which is referred to as an interposer andarranges semiconductor bumps as projection electrodes on another mainsurface (rear face) side which faces one main surface of the printedwiring board.

[0006] Further, in the CSP type semiconductor device, a CSP typesemiconductor device having a new package structure which ismanufactured by a manufacturing technique which integrates a waferprocess (preceding step) and a package process (succeeding step) (waferlevel CSP type semiconductor device) has been commercialized. In thiswafer level CSP type semiconductor device, a planer size of the packageis substantially equal to a planer size of the semiconductor chip andhence, it is possible to realize the miniaturization and the reductionof cost compared to the CSP type semiconductor device (chip level CSPtype semiconductor device) which is manufactured by applying thepackaging process to each semiconductor chip divided from asemiconductor wafer.

[0007] The wafer-level CSP type semiconductor device substantiallyincludes a semiconductor chip layer, a rewiring layer (pad rearranginglayer) which is formed over one main surface of the semiconductor chiplayer and solder bumps which are arranged on the rewiring layer asprojection electrodes. The semiconductor chip layer is substantiallyconstituted of a semiconductor substrate, a multilayered wiring layerwhich is formed by stacking insulation layers and wiring layersrespectively in a plural stages on one main surface of the semiconductorsubstrate and a surface protective film which is formed such that thesurface protective film covers the multilayered wiring layer. Electrodepads are formed over an uppermost wiring layer out of the multilayeredwiring layer and bonding openings which expose the electrode pads areformed in the surface protective film. The rewiring layer is a layerwhich is served for forming electrode pads having a wider arrangementpitch with respect to the electrode pads of the semiconductor chiplayer. The electrode pads of the rewiring layer are electricallyconnected with the corresponding electrode pads of the semiconductorchip layer and are arranged at the same arrangement pitch withconnecting portions which are arranged on a region of the printed wiringboard on which the wafer level CSP type semiconductor devices aremounted. The solder bumps are arranged on the electrode pads of therewiring layer and are electrically and mechanically connected with theelectrode pads of the rewiring layer. The wafer level CSP typesemiconductor devices are described in “Nikkei Micro Device” [1998,August issue, pp44-71] published by Nikkei Bp Ltd., for example.

[0008] Here, in this specification, the wafer level CSP typesemiconductor device is also defined as a type of semiconductor chip.

[0009] The ACF mounting method is a method which uses semiconductorchips having stud bumps made of gold (Au), for example, as projectionelectrodes on one main surface and mounts the semiconductor chips on aprinted wiring board by compression-bonding the semiconductor chipswhile heating the semiconductor chips in a state that an anisotropicconductive resin film (ACF) is interposed between the printed wiringboard and the semiconductor chips as an adhesive resin. The anisotropicconductive resin film is a sheet which is produced by forming aninsulation resin in which a large number of conductive particles aredispersed therein into a sheet shape, wherein an epoxy-basedthermosetting type resin, for example, is used as the insulation resin.The stud bumps made of Au constitute balls by melting distal ends of Auwires and, thereafter, the balls are compression-bonded under heat toelectrode pads which are arranged on one main surface of thesemiconductor chip while applying ultrasonic vibration and, thereafter,ball portions are cut out from the Au wire thus forming thesemiconductor chip. The ACF mounting method is, for example, describedin Japanese unexamined patent publication 345041/1992 and Japaneseunexamined patent publication 175280/1993.

[0010] As a mounting method which mounts semiconductor chips (stud-bumpconnection semiconductor chips) using thermo compression bonding as inthe case of ACF mounting method, besides the ACF mounting method, thereexists an NCF mounting method which uses an insulation resin film inwhich conductive particles are not mixed (NCF: non-conductive film) asan adhesive resin, an ACP mounting method which uses a paste-likeanisotropic conductive resin (ACP: anisotropic conductive paste) and thelike.

DISCLOSURE OF THE INVENTION

[0011] Here, the reduction of cost is also requested with respect to theMCM which adopts the flip-chip packaging technique. To achieve thereduction of cost of MCM, it is effective to use existing semiconductorchips as much as possible while obviating the development ofsemiconductor chips for an exclusive use.

[0012] To use the existing semiconductor chips as much as possible, itis necessary to mount semiconductor chips which differ in types of bumpsin a mixed form. However, with respect to the conventional MCM, it hasbeen generally manufactured using the semiconductor chips of the sametype and hence, a process which manufactures the MCM in a state that thesemiconductor chips which differ in types of bumps are mounted on thesame printed wiring board in a mixed form has not been established.

[0013] Accordingly, inventors have reviewed the MCM which mounts twotypes of semiconductor chips which differ in types of bumps (solder-bumpconnection semiconductor chips, stud-bump connection semiconductorchips) on the same printed wiring board in a mixed form and have foundout following drawbacks.

[0014] (1) Mounting of the solder-bump connection semiconductor chips isperformed by melting the solder bumps based on a reflow method andhence, when the stud-bump connection semiconductor chips are mountedusing the ACF mounting method before mounting the solder-bump connectionsemiconductor chips, heat which is used at the time of mounting thesolder-bump connection semiconductor chips is applied to the anisotropicconductive resin. Since the anisotropic conductive resin uses anepoxy-based thermosetting type insulation resin as a main material, whenthe heat of high temperature is applied to the anisotropic conductiveresin after thermosetting, bonding in the inside of the resin is brokenand cracks are liable to be easily generated. According to the studycarried out by the inventors, the generation of cracks remarkably tookplace by applying the heat having a temperature higher than a curingtemperature of the resin.

[0015] The connection between the connecting portions of the printedwiring board and the stud bumps is held by a thermo shrinking force(shrinking force which is generated when the resin returns to anordinary temperature state from a heated state), a thermo settingshrinking force (shrinking force which is generated when thethermosetting resin is cured) and the like of the anisotropic conductiveresin which is interposed between the printed wiring board and thestud-bump connection semiconductor chips. Accordingly, when cracks aregenerated in the anisotropic conductive resin, the shrinking forces arelowered and this causes a connection failure whereby the reliability ofthe MCM is lowered. Accordingly, when the solder-bump connectionsemiconductor chips and the stud-bump connection semiconductor chipswhich are mounted by the ACF mounting method are mounted in a mixedform, an idea to prevent applying of heat of equal to or more than thecuring temperature to the anisotropic conductive resin as much aspossible becomes necessary.

[0016] (2) As a method which mounts the stud-bump connectionsemiconductor chips, besides a method which uses an adhesive resin suchas the ACF mounting method, there exists a method which performsmounting of the semiconductor chips using previous solder (bondingmaterial). In this case, by collectively mounting the stud-bumpconnection semiconductor chips with the solder-bump connectionsemiconductor chips, a mounting step can be simplified. However, whenthe solder-bump connection semiconductor chips and stud-bump connectionsemiconductor chips are collectively mounted, a yield rate of the MCM islowered. The reason is as follows.

[0017] The stud-bump connection semiconductor chips do not have arewiring layer and hence, the arrangement pitch of electrode pads towhich the bumps are connected is narrower than the arrangement pitch ofthe electrode pads of the solder-bump connection semiconductor chip.Since the planer size of the electrode pads of the chip is regulated bythe arrangement pitch of the electrode pads, the planer size becomessmaller corresponding to narrowing of the arrangement pitch of theelectrode pads. Further, the size of the bump is regulated by the planersize of the electrode pad and hence, the size of the bump becomessmaller corresponding to the decrease of the planer size of theelectrode pad. That is, with respect to the stud-bump connectionsemiconductor chips with the narrow arrangement pitch of the electrodepads, since the stud bumps are also small and hence, the connectionfailure derived from the positional displacement at the time of mountingis liable to easily occur.

[0018] Further, the stud bumps are formed of metal having a high meltingpoint such as gold, aluminum or the like, for example, compared to Pb—Snbased solder or other solder. Accordingly, in mounting the semiconductorchips onto the printed wiring board, the stud bumps cannot be melted.This is because that when the heat treatment of a level which meltsmetal having a high melting point such as gold or aluminum is applied tothe semiconductor chip, the electric characteristics of thesemiconductor chip is largely changed before and after the heattreatment and hence, there arises a drawback that desiredcharacteristics cannot be obtained. Accordingly, when the semiconductorchips having stud bumps made of gold or aluminum are mounted using theprevious solder (bonding material), the mounting is performed by meltingonly the previous solder. When the mounting of the semiconductor chipsusing the above-mentioned method is performed, compared to the CCBmethod which mounts the semiconductor chips by melting the solder bumps,a position correction force which is obtained by a surface tension whichthe melted solder has becomes weak.

[0019] In this manner, since the semiconductor chips having the studbumps (the stud-bump connection semiconductor chips) are formed over thesmall pads and hence, due to the fact that the diameter of the studbumps is made small and the fact that the mounting is performed bymelting only the previous solder so that the strong re-correction forcecannot be obtained, there arises a drawback that the connection failureattributed to the positional displacement at the time of mounting isliable to easily occur.

[0020] It is an object of the present invention to provide a techniquewhich is capable of enhancing the reliability of an electronic device.

[0021] It is another object of the present invention to provide atechnique which is capable of enhancing a manufacturing yield rate ofelectronic devices.

[0022] The above-mentioned and other objects and novel features of thepresent invention will become apparent from the description of thisspecification and attached drawings.

[0023] To briefly explain the summary of typical inventions among theinventions described in this application, they are as follows.

[0024] (1) A manufacturing method of an electronic device comprises thesteps of:

[0025] preparing a printed wiring board having a first region and asecond region which differ from each other on one main surface thereof,a first electronic component having a plurality of first projectionelectrodes on one main surface thereof, and a second electroniccomponent having a plurality of second projection electrodes which havea melting point higher than a melting point of the first projectionelectrodes on one main surface thereof;

[0026] mounting the first electronic component on the first region ofone main surface of the printed wiring board by melting the plurality offirst projection electrodes; and

[0027] mounting the second electronic component on the second region ofone main surface of the printed wiring board by compression-bonding thesecond electronic component while heating in a state that an adhesiveresin is interposed between the second region of one main surface of theprinted wiring board and one main surface of the second electroniccomponent,

[0028] wherein the step of mounting the second electronic component isperformed after the step of mounting the first electronic component.

[0029] The adhesive resin is a thermosetting insulation resin, theplurality of first projection electrodes are solder bumps, and theplurality of second projection electrodes are stud bumps.

[0030] An arrangement pitch of the plurality of second projectionelectrodes is smaller than an arrangement pitch of the plurality offirst projection electrodes.

[0031] The first and the second electronic components are formed of asemiconductor chip in which a circuit is incorporated.

[0032] The first electronic component is formed of a semiconductor chipwhich includes a semiconductor substrate, a plurality of semiconductorelements which are formed over one main surface of the semiconductorsubstrate, a plurality of first electrode pads which are formed over onemain surface of the semiconductor substrate, a plurality of secondelectrode pads which are formed as a layer above the first electrodepads and are respectively electrically connected to the plurality offirst electrode pads, the plurality of second electrode pads beingarranged at an arrangement pitch wider than an arrangement pitch of theplurality of first electrode pads, and the plurality of first projectionelectrodes which are respectively connected to the plurality of secondelectrode pads, and

[0033] the second electronic component is formed of a semiconductor chipwhich includes a semiconductor substrate, a plurality of semiconductorelements which are formed over one main surface of the semiconductorsubstrate, a plurality of electrode pads which are formed over one mainsurface of the semiconductor substrate, and the plurality of secondprojection electrodes which are respectively connected to the pluralityof electrode pads.

[0034] The first electronic component is a semiconductor device whichpackages a semiconductor chip incorporating a circuit therein, and thesecond electronic component is a semiconductor chip incorporating acircuit therein.

[0035] (2) An electronic device comprises:

[0036] a printed wiring board having a first region and a second regionwhich differ from each other;

[0037] a first electronic component which is mounted on the first regionby way of a plurality of first projection electrodes; and

[0038] a second electronic component which is mounted on the secondregion by way of a plurality of second projection electrodes which havea melting point higher than a melting point of the first projectionelectrodes.

[0039] The first projection electrodes are solder bumps and the secondprojection electrodes are stud bumps.

[0040] An arrangement pitch of the plurality of second projectionelectrodes is smaller than an arrangement pitch of the plurality offirst projection electrodes.

[0041] The first and the second electronic components are formed of asemiconductor chip in which a circuit is incorporated.

[0042] The first electronic component is formed of a semiconductor chipwhich includes a semiconductor substrate, a plurality of semiconductorelements which are formed over one main surface of the semiconductorsubstrate, a plurality of first electrode pads which are formed over onemain surface of the semiconductor substrate, a plurality of secondelectrode pads which are formed as a layer above the first electrodepads and are respectively electrically connected to the plurality offirst electrode pads, the plurality of second electrode pads beingarranged at an arrangement pitch wider than an arrangement pitch of theplurality of first electrode pads, and the plurality of first projectionelectrodes which are respectively connected to the plurality of secondelectrode pads, and

[0043] the second electronic component is formed of a semiconductor chipwhich includes a semiconductor substrate, a plurality of semiconductorelements which are formed over one main surface of the semiconductorsubstrate, a plurality of electrode pads which are formed over one mainsurface of the semiconductor substrate, and the plurality of secondprojection electrodes which are respectively connected to the pluralityof electrode pads.

[0044] The first electronic component is a semiconductor device whichpackages a semiconductor chip incorporating a circuit therein, and thesecond electronic component is a semiconductor chip incorporating acircuit therein.

[0045] (3) A manufacturing method of an electronic device comprises thesteps of:

[0046] (a) preparing a printed wiring board having a first region and asecond region which differ from each other on one main surface thereof,wherein a plurality of first connecting portions are arranged over thefirst region and a plurality of second connecting portions are arrangedover the second region, a first electronic component having a pluralityof first projection electrodes on one main surface thereof, and a secondelectronic component having a plurality of second projection electrodeswhich have a melting point higher than a melting point of the firstprojection electrodes on one main surface thereof;

[0047] (b) electrically connecting the plurality of second connectingportions and the plurality of second projection electrodes to each otherby melting a bonding material having a melting point higher than amelting point of the first projection electrodes and lower than amelting point of the second projection electrodes; and

[0048] (c) electrically connecting the plurality of first connectingportions and the plurality of first projection electrodes by melting theplurality of first projection electrodes, wherein

[0049] the step (b) is performed before the step (c).

[0050] The plurality of first projection electrodes are solder bumps,and the plurality of second projection electrodes are stud bumps.

[0051] An arrangement pitch of the plurality of second projectionelectrodes is smaller than an arrangement pitch of the plurality offirst projection electrodes.

[0052] The first and the second electronic components are formed of asemiconductor chip in which a circuit is incorporated.

[0053] The first electronic component is formed of a semiconductor chipwhich includes a semiconductor substrate, a plurality of semiconductorelements which are formed over one main surface of the semiconductorsubstrate, a plurality of first electrode pads which are formed over onemain surface of the semiconductor substrate, a plurality of secondelectrode pads which are formed as a layer above the first electrodepads and are respectively electrically connected to the plurality offirst electrode pads, the plurality of second electrode pads beingarranged at an arrangement pitch wider than an arrangement pitch of theplurality of first electrode pads, and the plurality of first projectionelectrodes which are respectively connected to the plurality of secondelectrode pads, and

[0054] the second electronic component is formed of a semiconductor chipwhich includes a semiconductor substrate, a plurality of semiconductorelements which are formed over one main surface of the semiconductorsubstrate, a plurality of electrode pads which are formed over one mainsurface of the semiconductor substrate, and the plurality of secondprojection electrodes which are respectively connected to the pluralityof electrode pads.

[0055] The first electronic component is a semiconductor device whichpackages a semiconductor chip incorporating a circuit therein, and thesecond electronic component is a semiconductor chip incorporating acircuit therein.

[0056] (4) An electronic device comprises:

[0057] a printed wiring board having a first region and a second regionwhich differ from each other, wherein a plurality of first connectingportions are arranged in the first region and a plurality of secondconnecting portions are arranged in the second region;

[0058] a first electronic component having a plurality of firstprojection electrodes on one main surface thereof; and

[0059] a second electronic component having a plurality of secondprojection electrodes which have a melting point higher than a meltingpoint of the first projection electrodes on one main surface thereof,wherein

[0060] the plurality of first projection electrodes are respectivelyconnected to the plurality of first connecting portions, and

[0061] the plurality of second projection electrodes are respectivelyconnected to the plurality of second connecting portions by way of abonding material having a melting point higher than a melting point ofthe first projection electrodes and lower than a melting point of thesecond projection electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0062]FIG. 1 is a plan view of an MCM which constitutes an embodiment 1of the present invention.

[0063]FIG. 2 is a bottom view of the MCM shown in FIG. 1.

[0064]FIG. 3 is a cross-sectional view of an essential part of the MCMshown in FIG. 1 ((a) being a cross-sectional view taken along a line A-Ain FIG. 1, (b) being a cross-sectional view taken along a line B-B inFIG. 1).

[0065]FIG. 4 is a cross-sectional view in an enlarged form of a portionof FIG. 3(a).

[0066]FIG. 5 is a cross-sectional view in an enlarged form of a portionof FIG. 3(b).

[0067]FIG. 6 is a plan view of a semiconductor chip (stud-bumpconnection semiconductor chip) shown in FIG. 1.

[0068]FIG. 7 is a plan view of a semiconductor chip (solder-bumpconnection semiconductor chip) shown in FIG. 1.

[0069]FIG. 8 is a cross-sectional view of an essential part of thesemiconductor chip shown in FIG. 7.

[0070]FIG. 9 is a plan view of a printed wiring board which can beobtained in a plural number at a time used in the manufacture of the MCMshown in FIG. 1.

[0071]FIG. 10 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 1 ((a) being across-sectional view taken at a position along a line A-A in FIG. 1, (b)being a cross-sectional view taken at a position along a line B-B inFIG. 1).

[0072]FIG. 11 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 1 ((a) being across-sectional view taken at a position along a line A-A in FIG. 1, (b)being a cross-sectional view taken at a position along a line B-B inFIG. 1).

[0073]FIG. 12 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 1 ((a) being across-sectional view taken at a position along a line A-A in FIG. 1, (b)being a cross-sectional view taken at a position along a line B-B inFIG. 1).

[0074]FIG. 13 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 1 ((a) being across-sectional view taken at a position along a line A-A in FIG. 1, (b)being a cross-sectional view taken at a position along a line B-B inFIG. 1).

[0075]FIG. 14 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 1 ((a) being across-sectional view taken at a position along a line A-A in FIG. 1, (b)being a cross-sectional view taken at a position along a line B-B inFIG. 1).

[0076]FIG. 15 is a cross-sectional view of an essential part of an MCMwhich constitutes an embodiment 2 of the present invention.

[0077]FIG. 16 is a plan view of an MCM which constitutes an embodiment 3of the present invention.

[0078]FIG. 17 is a cross-sectional view of an essential part of the MCMshown in FIG. 16 ((a) being a cross-sectional view taken along a lineC-C in FIG. 16, (b) being a cross-sectional view taken along a line D-Din FIG. 16).

[0079]FIG. 18 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 16 ((a) being across-sectional view taken at a position along a line C-C in FIG. 16,(b) being a cross-sectional view taken at a position along a line D-D inFIG. 16).

[0080]FIG. 19 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 16 ((a) being across-sectional view taken at a position along a line C-C in FIG. 16,(b) being a cross-sectional view taken at a position along a line D-D inFIG. 16).

[0081]FIG. 20 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 16 ((a) being across-sectional view taken at a position along a line C-C in FIG. 16,(b) being a cross-sectional view taken at a position along a line D-D inFIG. 16).

[0082]FIG. 21 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 16 ((a) being across-sectional view taken at a position along a line C-C in FIG. 16,(b) being a cross-sectional view taken at a position along a line D-D inFIG. 16).

[0083]FIG. 22 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 16 ((a) being across-sectional view taken at a position along a line C-C in FIG. 16,(b) being a cross-sectional view taken at a position along a line D-D inFIG. 16).

[0084]FIG. 23 is a cross-sectional view of an essential part forexplaining the manufacture of the MCM shown in FIG. 16 ((a) being across-sectional view taken at a position along a line C-C in FIG. 16,(b) being a cross-sectional view taken at a position along a line D-D inFIG. 16).

[0085]FIG. 24 is a cross-sectional view of an essential part forexplaining the manufacture of an MCM of an embodiment 4 of the presentinvention ((a) being a cross-sectional view taken at the same positionas a line C-C in FIG. 16, (b) being a cross-sectional view taken at thesame position as a line D-D in FIG. 16).

[0086]FIG. 25 is a cross-sectional view of an essential part forexplaining the manufacture of an MCM of the embodiment 4 of the presentinvention((a) being a cross-sectional view taken at the same position asa line C-C in FIG. 16, (b) being a cross-sectional view taken at thesame position as a line D-D in FIG. 16).

[0087]FIG. 26 is a cross-sectional view of an essential part forexplaining the manufacture of an MCM of an embodiment 5 of the presentinvention((a) being a cross-sectional view taken at the same position asa line C-C in FIG. 16, (b) being a cross-sectional view taken at thesame position as a line D-D in FIG. 16).

[0088]FIG. 27 is a cross-sectional view of an essential part forexplaining the manufacture of an MCM of the embodiment 5 of the presentinvention ((a) being a cross-sectional view taken at the same positionas a line C-C in FIG. 16, (b) being a cross-sectional view taken at thesame position as a line D-D in FIG. 16).

BEST MODE FOR CARRYING OUT THE INVENTION

[0089] Embodiments of the present invention are explained in detail inconjunction with attached drawings hereinafter. In all drawings forexplaining the embodiments of the present invention, same symbols aregiven to parts having identical functions and their repeated explanationis omitted. Further, in some cross-sectional views, to facilitate theunderstanding of the drawings, hatching which indicates a cross sectionis partially omitted.

EMBODIMENT 1

[0090]FIG. 1 is a plan view of an MCM (electronic device) whichconstitutes an embodiment 1 of the present invention, FIG. 2 is a bottomview of the MCM shown in FIG. 1, FIG. 3 is a cross-sectional view of anessential part of the MCM shown in FIG. 1 ((a) being a cross-sectionalview taken along a line A-A in FIG. 1, (b) being a cross-sectional viewtaken along a line B-B in FIG. 1), FIG. 4 is a cross-sectional view inan enlarged form of a portion of FIG. 3(a), FIG. 5 is a cross-sectionalview in an enlarged form of a portion of FIG. 3(b), FIG. 6 is a planview of a semiconductor chip (stud-bump connection semiconductor chip)shown in FIG. 1, FIG. 7 is a plan view of a semiconductor chip(solder-bump connection semiconductor chip) shown in FIG. 1, and FIG. 8is a cross-sectional view of an essential part of the semiconductor chipshown in FIG. 7.

[0091] As shown in FIG. 1 to FIG. 3, an MCM-1A of this embodiment isconfigured such that one semiconductor chip (stud-bump connectionsemiconductor chip) 3 and two semiconductor chips (solder-bumpconnection semiconductor chips) 4 are mounted on one main surface 2Xside of a printed wiring board 2 as electronic components, a pluralityof solder bumps 11 which constitute external connection terminals arearranged on another main surface (back face) 2Y side of the printedwiring board 2 which faces one main surface 2X in an opposed manner. Thesemiconductor chip 3 incorporates a control circuit, for example,therein, while the semiconductor chip 4 incorporates an SDRAM(Synchronous Dynamic Random Access Memory) of 64 megabits, for example,as a memory circuit.

[0092] The printed wiring board 2 is configured to include, mainly arigid substrate (core substrate) 20, soft layers 21, 21B which areformed over both faces of the rigid substrate 20 in an opposed manner bya build-up method, and protective films 24, 26 which are formed suchthat these films cover the soft layers 21, 21B. The rigid substrate 20and the soft layers 21, 21B constitute, although not shown in detail inthe drawings, a multi-layered wiring structure, for example. Respectiveinsulation layers of the rigid substrate 20 are formed of a highlyresilient resin substrate which is produced by impregnating anepoxy-based or polyimide-based resin into glass fiber, for example.Respective insulation layers of the soft layers 21, 21B are formed of anepoxy-based low resilient resin, for example. Respective wiring layersof the rigid substrate 20 and the soft layers 21, 21B are formed of ametal film made of copper (Cu), for example. The protective films 24 and26 are formed of a polyimide-based resin, for example. The protectivefilm 24 is formed mainly for the purpose of protecting wiring formedover an uppermost wiring layer of the soft layer 21, wherein the softlayer 21 plays the role of ensuring an adhesive force with an adhesiveresin at the time of mounting with respect to the semiconductor chip 3and controls spreading of solder wetting at the time of mounting withrespect to the semiconductor chip 4. The protective film 26 is formedmainly for the purpose of protecting wiring formed over an uppermostwiring layer of the soft layer 21B, wherein the protective film 26controls spreading of solder wetting at the time of forming bumps withrespect to solder bumps 11.

[0093] Planer shapes of the semiconductor chip 3 and the semiconductorchip 4 are formed in a quadrangular shape. In this embodiment, thesemiconductor chip 3 is formed in a square shape of 6.8 mm×6.8 mm, forexample, while the semiconductor chip 4 is formed in a rectangular shapeof 5.99×8.7 mm, for example. Further, in this embodiment, thesemiconductor chip 3 and the semiconductor chip 4 are formed with athickness of approximately 0.4 mm, for example.

[0094] The semiconductor chip 3 is, although not limited, mainlyconstituted of a semiconductor substrate, a plurality of semiconductorelements which are formed over one main surface of the semiconductorsubstrate, a multi-layered wiring layer which is formed by stackinginsulation layers and wiring layers respectively in a plural stages onone main surface of the semiconductor substrate, and a surfaceprotective film (final protective film) which is formed so as to coverthe multi-layered wiring layer. The semiconductor substrate is formed ofsingle crystalline silicon, for example, the insulation layers areformed of a silicon oxide film, for example, and the wiring layers areformed of a metal film made of aluminum (Al) or an aluminum alloy, forexample. The surface protective film is formed of an insulation filmmade of silicon oxide or silicon nitride and an organic insulation film,for example.

[0095] On one main surface 3X out of one main surface 3X and anothermain surface (back face) of the semiconductor chip 3 which face eachother in an opposed manner, a plurality of electrode pads 5 are formed.The plurality of electrode pads 5 are formed over the uppermost wiringlayer of the multilayered wiring layer of the semiconductor chip 3 andare exposed through bonding openings formed in the surface protectivefilm of the semiconductor chip 3. The plurality of electrode pads 5 arearranged along respective sides of the semiconductor chip 3. A planershape of each one of the plurality of electrode pads 5 is formed in aquadrangular shape of 70 [μm]×70 [μm], for example. Further, theplurality of electrode pads 5 are respectively arranged at anarrangement pitch of approximately 85 [μm], for example.

[0096] On one main surface 3X of the semiconductor chip 3, stud bumps 7made of, for example, gold (Au) are arranged as projection electrodes.The plurality of stud bumps 7 are respectively arranged on the pluralityof electrode pads 5 arranged on one main surface 3X of the semiconductorchip 3 and are electrically and mechanically connected with theelectrode pads 5. The stud bumps 7 are, for example, formed by a ballbonding method which uses Au wires and ultrasonic vibration in heatcompression bonding. The ball bonding method is a method in which ballsare formed over distal end portions of the Au wires and, thereafter, theballs are compression-bonded with heat to the electrode pads of the chipby applying the ultrasonic vibration and, thereafter, the Au wires arecut out from the ball portions. Accordingly, the stud bumps formed overthe electrode pads are firmly connected to the electrode pads.

[0097] The semiconductor chip 4 is, as shown in FIG. 8, mainlyconstituted of a semiconductor chip layer 38, a rewiring layer (padrewiring layer) 39 which is formed over one main surface of thissemiconductor chip layer 38 and a plurality of soldering bumps 8 whichare arranged on this rewiring layer 39.

[0098] The semiconductor chip layer 38 is mainly constituted of asemiconductor substrate 30, a multilayered wiring layer 31 in whichinsulation layers and wiring layers are respectively stacked in pluralstages on one main surface of this semiconductor substrate 30 and asurface protective film 33 which is formed so as to cover themultilayered wiring layer 31. The semiconductor substrate 30 is formedof single crystalline silicon, for example, the insulation layers of themultilayered wiring layer 31 are formed of an oxide silicon film, forexample, the wiring layers of the multilayered wiring layer 31 areformed of an aluminum (Al) film or an aluminum alloy film, for example,and the surface protective film 33 is formed of a silicon nitride film,for example.

[0099] On a center portion of one main surface of the semiconductor chiplayer 38, a plurality of electrode pads 32 which are arranged along thelong-side direction of one main surface 4X of the semiconductor chip 4are formed and arranged in a row along input/output circuitsemiconductor elements formed over one main surface of the semiconductorsubstrate 30. The plurality of respective electrode pads 32 are formedover an uppermost wiring layer of the multilayered wiring layer 31. Theuppermost wiring layer of the multilayered wiring layer 31 is coveredwith the surface protective film 33 which is formed above the uppermostwiring layer and openings which expose surfaces of the electrode pads 32are formed in the surface protective film 33. A planer shape of theplurality of respective electrode pads 32 is formed in a quadrangularshape of 30[μm]×30[μm], for example. Further, the plurality ofrespective electrode pads 32 are arranged at an arrangement pitch ofapproximately 40[μm], for example.

[0100] The rewiring layer 39 is mainly constituted of an insulationlayer 34 which is formed over the surface protective film 33, aplurality of lines 35 which extend on the insulation layer 34, aninsulation layer 36 which is formed over the insulation layer 34 so asto cover the plurality of lines 35, and a plurality of inspectionelectrode pads 37 and a plurality of electrode pads 6 which are formedabove the insulation layer 36.

[0101] Respective one end sides of the plurality of lines 35 arerespectively electrically and mechanically connected to the plurality ofelectrode pads 32 through openings formed in the insulation layer 34 andopenings formed in the surface protective film 33. Substantially half ofthe plurality of lines 35 have respective another end sides thereofpulled out to one long side out of two long sides which face each otherin an opposed manner on one main surface 4X of the semiconductor chip 4,while remaining lines 35 have end sides thereof pulled out to anotherlong side.

[0102] The plurality of respective inspection electrode pads 37 areelectrically and mechanically connected to respective one end sides ofthe plurality of lines 35 through openings formed in the insulationlayer 36. The plurality of respective electrode pads 6 are electricallyand mechanically connected to respective one end sides of the pluralityof lines 35 through openings 36 a formed in the insulation layer 36.

[0103] To the plurality of respective electrode pads 6, the plurality ofsolder bumps 8 which are arranged on the rewiring layer 39 areelectrically and mechanically connected. The plurality of respectivesolder bumps 8 are formed of a metal member (Pb free material) made ofSn-1 [wt %] Ag(silver)-0.5 [wt %] Cu(copper) composition having amelting point of approximately 230° C., for example.

[0104] The rewiring layer 39 is a layer for rearranging the electrodepads 6 having a wide arrangement pitch with respect to the electrodepads 32 of the semiconductor chip layer 38, wherein the electrode pads 6of the rewiring layer 39 are arranged at the arrangement pitch equal toan arrangement pitch of connecting portions of the printed wiring boardon which the semiconductor chip 4 is mounted.

[0105] The plurality of respective electrode pads 6 are, not limitedspecifically, arranged in a two row state along respective long sides attwo long sides which face each other in an opposed manner on one mainsurface 4X of the semiconductor chip 4. The electrode pads 6 of each roware arranged at the arrangement pitch of approximately 0.5 mm, forexample. A planer shape of the plurality of respective electrode pads 6is formed in a circular shape having a diameter of approximately 0.25mm, for example.

[0106] In the rewiring layer 39, to alleviate the concentration ofstress generated by the difference of thermal expansion between theinsulation layer 34 on the solder bumps 8, the insulation layer 36 andthe printed wiring board after mounting the semiconductor chip 4 on theprinted wiring board, the insulation layer 34 and the insulation layer36 are respectively formed of a material which exhibits the lowresiliency compared to the silicon nitride film or the silicon oxidefilm and, at the same time, are formed with a thickness larger than athickness of the surface protective film 34. In this embodiment, theinsulation layers 34 and 36 are formed of a polyimide-based resin, forexample.

[0107] By forming lines exhibiting lower resistance, lower capacitanceand lower impedance than the multilayered wiring layer 31 as the lines35 which form the rewiring layer 39, the arrangement of the electrodepads can be determined with more freedom. Accordingly, the lines 35 areformed of a copper (Cu) film having the high conductivity, for example.Further, it is preferable that the lines 35 are formed of a conductivefilm having a large thickness compared to the electrode pads 32 whichconstitute portions of the multilayered wiring layer 31. Still further,it is preferable to use an organic insulation film having a lowdielectric constant compared to an inorganic interlayer insulation filmwhich is formed between the multilayer wiring layer 31 as the insulationfilm 36 which covers the lines 35. Although not limited specifically, toensure the wettability at the time of forming the solder bumps 8, theelectrode pads 6 are formed of a laminated film which is produced bysequentially stacking respective films consisting of a chromium (Cr)film, an alloy film having the composition of nickel (Ni)-copper (Cu)and a gold (Au) film.

[0108] As shown in FIG. 3 to FIG. 5, although not shown in detail in thedrawings, on one main surface 2X of the printed wiring board 2, aplurality of lines 22, a plurality of lines 23 and the like are formed.The plurality of lines 22 and 23 are formed over an uppermost wiringlayer of the soft layer 21. The plurality of lines 22 have connectingportions 22 a which are respectively formed of portions of the lines 22,wherein the respective connecting portions 22 a are exposed throughopenings formed in the protective film 24. The respective connectingportions 22 a of the plurality of lines 22 are arranged in a state thatthe connecting portions 22 a correspond to the plurality of electrodepads 5 of the semiconductor chip 3.

[0109] The plurality of lines 23 have connecting portions 23 a which arerespectively formed of portions of the lines 23, wherein the respectiveconnecting portions 23 a are exposed through openings formed in theprotective film 26. The respective connecting portions 23 a of theplurality of lines 23 are arranged in a state that the connectingportions 23 a correspond to the plurality of electrode pads 6 of thesemiconductor chip 4.

[0110] On another main surface (back face) of the printed wiring board 2which faces one main surface 2X, the plurality of electrode pads 25 areformed. The electrode pads 25 are formed over the uppermost wiring layerof the soft layer 21B.

[0111] To the plurality of respective electrode pads 25, the pluralityof solder bumps 11 which are arranged on the back face side of theprinted wiring board 2 as external connection terminals are electricallyand mechanically connected. The plurality of respective solder bumps 11are formed of a metal member (Pb—Sn eutectic material) made of 37 [wt %]Pb(lead)-63 [wt %]Sn(tin) composition having a melting point ofapproximately 183° C., for example.

[0112] The semiconductor chip 3 is mounted in a state that one mainsurface 3X thereof faces one main surface 2X of the printed wiring board2. An anisotropic conductive resin 9, for example, is interposed betweenthe semiconductor chip 3 and the printed wiring board 2 as an adhesiveresin and the semiconductor chip 3 is fixed to the printed wiring board2 by adhesion using the anisotropic conductive resin 9. As theanisotropic conductive resin 9, for example, a material which isproduced by mixing a large number of conductive particles in the insideof an epoxy-based thermosetting insulation resin is used.

[0113] The plurality of stud bumps 7 are arranged between the respectiveelectrode pads 5 of the semiconductor chip 3 and the respectiveconnecting portions 22 a of the printed wiring board 2, wherein therespective pads 5 and the respective connecting portions 22 a areelectrically connected to each other. The stud bumps 7 arecompression-bonded to the connecting portions 22 a of the printed wiringboard 22 by a thermo shrinking force (shrinking force which is generatedwhen the resin returns to an ordinary temperature state from a heatedstate), a thermo setting shrinking force (shrinking force which isgenerated when the thermosetting resin is cured) and the like of theanisotropic conductive resin 9 which is interposed between the printedwiring board 2 and the semiconductor chips 3. Here, between the studbumps 7 and the connecting portions 22 a of the printed wiring board 2,a portion of the conductive particles which are mixed in the anisotropicconductive resin 9 in a large number is interposed.

[0114] Recessed portions which indent in the depth direction of theprinted wiring board 2 are formed in the connecting portions 22 a of theprinted wiring board 2. In the inside of the recessed portions, the studbumps 7 and the connecting portions 22 a are connected. In this manner,by connecting the stud bumps 7 and the connecting portions 22 a in theinside of the recessed portions, it is possible to reduce a volume ofthe anisotropic conductive resin 9 between one main surface 2X of theprinted wiring board 2 and one main surface 3X of the semiconductor chip3 by an amount corresponding to an indenting quantity of the recessedportions.

[0115] Through openings formed in the protective film 24, the stud bumps7 are connected to the connecting portions 22 a which are arranged atbottoms of the openings. That is, the stud bumps 7 extend in the depthdirection from one main surface 2X of the printed wiring board 2 and areconnected to the connecting portions 22 a which are arranged atpositions deeper than one main surface 2X. In this manner, by arrangingthe connecting portions 22 a at the positions deeper than one mainsurface of the printed wiring board 2, it is possible to reduce a volumeof the anisotropic conductive resin 9 between one main surface 2X of theprinted wiring board 2 and one main surface 3X of the semiconductor chip3 by an amount corresponding to the depth from one main surface 2X ofthe printed wiring board 2 to the connecting portions 22 a.

[0116] The recessed portions of the connecting portions 22 a are formedbased on the resilient deformation of the connecting portion 22 and thesoft layer 21. The recessed portions which are formed due to theresilient deformation of the connecting portion 22 a and the soft layer21 can be formed by compression bonding force at the time of mountingthe semiconductor chip 3 to one main surface of the printed wiring board2. When the recessed portions are formed due to the resilientdeformation of the connecting portion 22 a and the soft layer 21, aresilient force of the connecting portions 22 a and the soft layer 21acts on the stud bumps 7 and hence, a compression force between the studbumps 7 and the connecting portions 22 a is increased.

[0117] Further, even when a gap between one main surface 2X of theprinted wiring board 2 and one main surface 3X of the semiconductor chip3 is widened due to the expansion of the anisotropic conductive resin 9in the thickness direction and the stud bumps 7 are moved upwardlycorrespondingly, the indenting amount of the recessed portions of theconnecting portions 22 a is changed due to the resilient restoring forceof the soft layer 21 following the movement of the stud bumps 7 andhence, it is possible to ensure the connection between the connectingportions 22 a of the printed wiring board 2 and the stud bumps 7.

[0118] The semiconductor chip 4 is mounted in a state that one mainsurface 4X thereof faces one main surface 2X of the printed wiring board2. The plurality of solder bumps 8 are respectively arranged between therespective electrode pads 6 of the semiconductor chip 4 and therespective connecting portions 23 a of the printed wiring board 2 so asto respectively electrically and mechanically connect the respectiveelectrode pads 6 and the respective connecting portions 23 a.

[0119] In a gap region defined between the semiconductor chip 4 and theprinted wiring board 2, an underfill resin 10 made of an epoxy-basedthermosetting insulation resin, for example, is filled (injected). Inthis manner, by filling the underfill resin 10 in the gap region definedbetween the semiconductor chip 4 and the printed wiring board 2, it ispossible to compensate for the mechanical strength of the solder bumps 8with the mechanical strength of the underfill resin 10 whereby it ispossible to suppress the rupture of the solder bumps 8 caused by thedifference in thermal expansion coefficient between the semiconductorchip 4 and the printed wiring board 2.

[0120] The plurality of stud bumps 7 are, as shown in FIG. 6, arrangedalong respective sides of one main surface 3X of the semiconductor chip3. The arrangement pitch 7P of the stud bump 7 is set to approximately85 [μm], for example. The plurality of solder bumps 8 are, as shown inFIG. 7, arranged in two rows along respective long sides at two longsides which face each other on one main surface 4X of the semiconductorchip 4. The arrangement pitch 8P of the semiconductor pumps 8 in eachrow is set to approximately 0.5 mm, for example.

[0121] Next, the printed wiring board for taking plural pieces which isused in the manufacture of MCM-1A is explained in conjunction with FIG.9 (plan view).

[0122] As shown in FIG. 9, the printed wiring board 40 for taking pluralpieces is configured to include a plurality of board forming regions(product forming regions) 41 which are arranged in the longitudinaldirection at a given interval. In this embodiment, the printed wiringboard 40 includes three board forming regions 41, for example. In eachboard forming region 41, one chip mounting region 42 and two chipmounting regions 43 are provided. A semiconductor chip (stud-bumpconnection semiconductor chip) 3 is mounted on the chip mounting region42 and semiconductor chips (solder-bump connection semiconductor chips)4 are mounted on the chip mounting region 43.

[0123] Respective board forming regions 41 have peripheries thereofsurrounded by a separation region and hence, the board forming regions41 are spaced apart from each other. By cutting the separation region ofthe printed wiring board 40 for taking plural pieces using a cuttingtool which is called a bit, for example, the board forming regions 41are cut out to form the above-mentioned printed wiring boards 2. Theboard forming region 41 has the same constitution as the printed wiringboard 2.

[0124] Next, the manufacture of the MCM-1A is explained in conjunctionwith FIG. 10 to FIG. 14. FIG. 10 to FIG. 14 are cross-sectional views ofan essential part for explaining the manufacture of the MCM-1A ((a)being the cross-sectional view taken along a line A-A in FIG. 1 and (b)being the cross-sectional view taken along a line B-B in FIG. 1).

[0125] First of all, the printed wiring board 40 for taking pluralpieces shown in FIG. 9 is prepared and, at the same time, thesemiconductor chips (stud-bump connection semiconductor chips) 3 shownin FIG. 6 and the semiconductor chips (solder-bump connectionsemiconductor chips) 4 shown in FIG. 7 are prepared.

[0126] Next, as shown in FIG. 10, before mounting the semiconductorchips 4, the semiconductor chips 4 are collectively mounted on therespective chip mounting regions 43 of the plurality of board formingregions 41 on one main surface of the printed wiring board 40. Mountingof the semiconductor chips 4 are performed such that a flux is suppliedto the connecting portions 23 a arranged on the chip mounting regions 43by a screen printing method, for example, and, thereafter, thesemiconductor chips 4 are arranged on the respective chip mountingregions 43 of the plurality of board forming regions 41 such that thesolder bumps 8 are positioned on the connecting portions 23 a and,thereafter, the printed wiring board 40 is transferred to an infraredreflow furnace, for example, to melt the solder bumps 8 and, thereafter,the melted solder bumps 8 are solidified. The solder bumps 8 of thisembodiment are formed of a metal material of Sn-1% Ag-0.5% Cucomposition having the melting point of approximately 230° C. and hence,melting of the solder bumps 8 is performed under the reflow temperaturecondition in which a package surface temperature (board surfacetemperature) is set to approximately 260° C. The flux contains rosin, anactivator, an organic solvent and the like.

[0127] Next, as shown in FIG. 11, to the chip mounting regions 42 of theboard forming regions 41 on one main surface of the printed wiring board40, as an adhesive resin, the anisotropic conductive resin 9 which isformed into a film shape (sheet shape) is laminated. As the anisotropicconductive resin 9, for example, a material which is produced by mixinga large number of conductive particles in an epoxy-based thermosettinginsulation resin is used. Further, as the anisotropic conductive resin9, such a resin having a thermosetting temperature of approximately 160°C. is used.

[0128] Next, as shown in FIG. 12, on the chip mounting regions 42 of theboard forming regions 41 on one main surface of the printed wiring board40, the semiconductor chips 3 are arranged by way of the anisotropicconductive resin 9 using collets 49. The semiconductor chips 3 arearranged such that the stud pumps 7 are positioned above the connectingportions 22 a. Further, the arrangement of the semiconductor chips 3 is,although not shown in FIG. 12, performed in a state that the printedwiring board 40 is arranged on a heat stage 51 shown in FIG. 13.

[0129] Next, as shown in FIG. 13, the printed wiring board 40 is heatedby the heat stage 51, the semiconductor chip 3 is compression-bonded bya compression bonding tool 50 while being heated by the compressionbonding tool 50 thus connecting the stud bumps 7 to the connectingportions 22 a of the printed wiring board 40. Thereafter, thecompression-bonding state is held until the anisotropic conductive resin9 is cured. At this point of time, the stud bumps 7 are brought intopressure contact with the connecting portions 22 a. Curing of theanisotropic conductive resin 9 is performed under the condition of 180°C. for 20 seconds. Heating at this point of time is performed such thatthe temperature of the printed wiring board 40 is preliminarily raisedto approximately 65° C. and, thereafter, the heating is performed usingthe compression-bonding tool 50 which is heated up to 235° C.

[0130] The lamination of the anisotropic conductive resin 9, thearrangement of the semiconductor chip 3 by the collet 9 and thecompression bonding of the semiconductor chip 3 by thecompression-bonding tool 50 constitute one cycle and this one cycle isrepeatedly performed for every substrate forming region 41.

[0131] In this step, by making a depth from one main surface of theprinted wiring board 40 to the connecting portion 22 a smaller than aheight of the stud bumps 7, recessed portions are formed in the portionsof the connecting portions 22 a to which the stud bumps 7 a areconnected by the compression bonding of the semiconductor chip 3.Further, in the inside of the recessed portion, the connecting portion22 a of the printed wiring board 40 and the stud bump 7 are connected.Further, since the recessed portion is formed by the resilientdeformation of the connecting portion 22 a and the soft layer 21, theresilient force of the connecting portion 22 a and the soft layer 21acts on the stud bump 7.

[0132] Here, when the semiconductor chip (stud-bump connectionsemiconductor chip) 3 is mounted prior to mounting of the semiconductorchip (solder-bump connection semiconductor chip) 4, at the time ofmounting the semiconductor chip 4, heat which is higher than the curingtemperature of the anisotropic conductive film 9 is applied to theanisotropic conductive film 9 and hence, the bonding of the anisotropicconductive resin 9 is broken and cracks are liable to occur in theanisotropic conductive resin 9. However, according to this embodiment,by mounting the semiconductor chip 4 prior to mounting of thesemiconductor chip 3, it is possible to prevent the heat generated atthe time of mounting the semiconductor chip 4 from being applied to theanisotropic conductive resin 9 and hence, the cracks which occur in theanisotropic conductive resin 9. attributed to the bonding rupture in theinside of the resin can be suppressed.

[0133] Next, as shown in FIG. 14, an underfill resin 10 in a liquid formmade of an epoxy-based thermosetting insulation resin, for example, isfilled in a gap region defined between a chip mounting region 43 of onemain surface of the printed wiring board 40 and the semiconductor chip 4and, thereafter, is heated to be cured. Curing of the underfill resin 10is performed under the condition of an ambient temperature of 160° C.for two hours. As the underfill resin 10, a resin which exhibits thethermosetting temperature of approximately 120° C., for example, isused.

[0134] Here, although the heat generated when the underfill resin 10 iscured is applied to the anisotropic conductive resin 9, the temperatureat this point of time is substantially equal to the curing temperatureof the anisotropic conductive resin 9 and hence, there is no possibilitythat the anisotropic conductive resin 9 suffers from the bondingrupture.

[0135] Here, when the underfill resin 10 is filled after mounting thesemiconductor chip 4 and before mounting the semiconductor chip 3, dueto spreading of wetting of the underfill resin 10, there exists apossibility that the connecting portion 22 a of the chip mounting region42 is covered with the underfill resin 10 and hence, it is necessary towiden the distance between the chip mounting regions 42, 43. However, byfilling the underfill resin 10 after mounting the semiconductor chip 3as in the case of this embodiment, there is no possibility that theconnecting portion 22 a of the chip mounting region 42 is covered due tospreading of wetting of the underfill resin 10 and hence, it is possibleto narrow the distance between the chip mounting regions 42 and 43.

[0136] Next, ball-shaped solder bumps 11 are supplied to positions abovethe electrode pads 25 which are arranged on a back surface of theprinted wiring board 40 by a ball supply method, for example, and,thereafter, the solder bumps 11 are melted so as to electrically andmechanically connect the electrode pads 25 and the solder bumps 11.Since the solder bumps 11 of this embodiment are formed of a metalmaterial of Pb—Sn composition having a melting point of approximately183° C., melting of the solder bumps 11 is performed under the reflowtemperature condition in which the package surface temperature is set toapproximately 230° C.

[0137] Here, although the heat is applied to the anisotropic conductiveresin 9 when the solder bumps 11 are melted, the heat treatment at thispoint of time is performed at a low temperature and for a short timecompared to the heat treatment performed at the time of mounting thesemiconductor chip 4 and hence, the possibility that such heatinfluences the rupture of bonding of the anisotropic conductive resin 9is relatively small.

[0138] Next, the board forming regions 41 are cut out by cutting theseparation region of the printed wiring board 40 for taking pluralpieces using a cutting tool thus forming the printed wiring boards 2. Inthis state, the MCA-1A is also almost completed. Although theexplanation is made with respect to the example in which the boardforming regions 41 are cut out after forming the solder bumps 11 in thisembodiment, the formation of the solder bumps 11 may be performed aftercutting out the board forming regions 41.

[0139] In this manner, according to the present invention, it ispossible to obtain following advantageous effects.

[0140] (1) In the manufacture of the MCA-1A which mounts thesemiconductor chip (stud-bump connection semiconductor chip) 3 and thesemiconductor chips (solder-bump connection semiconductor chips) 4 in amixed form on the same printed wiring board 2, the semiconductor chip 3is mounted after mounting the semiconductor chips 4. Accordingly, it ispossible to prevent the heat generated at the time of mounting thesemiconductor chip 4 from being applied to the anisotropic conductiveresin 9 and hence, it is possible to suppress the occurrence of cracksin the anisotropic conductive resin 9 attributed to the rupture ofbonding inside the resin. As a result, lowering of the shrinking forceof the anisotropic conductive resin 9 can be suppressed and hence, theconnection failure between the stud bumps 7 and the connecting portions22 a of the printed wiring board 2 can be suppressed whereby thereliability of the MCA-1A can be enhanced.

[0141] Further, it is possible to mount the semiconductor chip 3 and thesemiconductor chips 4 on the same printed wiring board 2 in a mixed formwhile ensuring the reliability of connection due to the anisotropicconductive resin 9.

[0142] (2) In the manufacture of the MCM-1A, after mounting thesemiconductor chip 4, the underfill resin 10 is filled in the gap regiondefined between the printed wiring board 40 and the semiconductor chip3. Due to such a constitution, there is no possibility that theconnecting portion 22 a of the chip mounting region 42 is covered due tospreading of wetting of the underfill resin 10 and hence, it is possibleto narrow the distance between the chip mounting regions 42 and 43. As aresult, the MCM-1A can be miniaturized.

[0143] Here, the explanation is made with respect to the example inwhich the thermosetting insulation resin is used as the underfill resin10 in this embodiment, an ultraviolet ray curing insulation resin may beused as the underfill resin 10. In this case, the underfill resin 10 canbe cured without applying heat to the anisotropic conductive resin 9 andhence, the reliability of the MCM-1A can be further enhanced.

[0144] Further, although the explanation is made with respect to theexample in which the anisotropic conductive resin 9 in a film shape isused as the adhesive resin in this embodiment, for example, aninsulation resin film in which no conductive particles are mixed (NCF),an anisotropic conductive resin in a paste form (ACP) or the like may beused as the adhesive resin.

[0145] Further, the explanation is made with respect to the example inwhich the solder bumps which are made of the metal material (PB-freematerial) having the Sn-1% Ag-0.5% Cu composition is used as the solderbumps 8 in this embodiment, the solder bumps 8 may be formed of a metalmaterial having the same composition as the solder bumps 11.

EMBODIMENT 2

[0146]FIG. 15 is a cross-sectional view of an essential part of an MCMaccording to the second embodiment of the present invention.

[0147] As shown in FIG. 15, the MCM-1B of this embodiment substantiallyhas the same constitution as the MCM of the above-mentioned embodiment 1and differs from the MCM of the above-mentioned embodiment 1 withrespect to following constitutions.

[0148] That is, in place of the semiconductor chips (solder-bumpconnection semiconductor chips) 4, CSP-type semiconductor devices 60each of which packages a semiconductor chip are mounted on the printedwiring board 2.

[0149] The CSP-type semiconductor device 60 is configured to include aprinted wiring board 61, a semiconductor chip 64 which is arranged onone main surface side of the printed wiring board 61, bonding wires 66which electrically connect electrode pads 65 arranged on one mainsurface of the semiconductor chip and electrode pads 62 arranged on onemain surface of the printed wiring board 61, a resin sealing body 67which seals the semiconductor chip 64 and the bonding wires 66, and aplurality of solder bumps 68 which are arranged as projection electrodeson another main surface (back surface) side which faces one main surfaceof the printed wiring board 61. The CSP-type semiconductor device 60 ismounted on the printed wiring board 2 by melting the solder bumps 68 inthe same manner as the semiconductor chips 4.

[0150] Also in the MCM-1B having such a constitution, by mounting theCSP-type semiconductor device 60 in advance before mounting thesemiconductor chip (stud-bump connection semiconductor chip) 3, it ispossible to obtain advantageous effects similar to those of the previousembodiments.

EMBODIMENT 3

[0151]FIG. 16 is a plan view of an MCM which constitutes an embodiment 3of the present invention. FIG. 17 is a cross-sectional view of anessential part of the MCM shown in FIG. 16 ((a) being a cross-sectionalview taken along a line C-C in FIG. 16, (b) being a cross-sectional viewtaken along a line D-D in FIG. 16).

[0152] As shown in FIG. 16 and FIG. 17, the MCM-1C of this embodimenthas substantially the same constitution as the MCM of theabove-mentioned embodiment 1 and differs from the MCM of theabove-mentioned embodiment 1 with respect to following constitutions.

[0153] That is, the stud bump 7 is electrically and mechanicallyconnected to the connecting portion 22 a of the printed wiring board 2by way of a bonding material 52. Further, in a gap region definedbetween the semiconductor chip (stud-bump connection semiconductor chip)3 and the printed wiring board 2, to suppress the rupture of thesemiconductor chip 3 caused by the concentration of the thermal stressattributed to the difference in thermal expansion coefficient betweenthe printed wiring board 2 and the semiconductor chip 3, the underfillresin 10 is filled in the same manner as the semiconductor chip(solder-bump connection semiconductor chip) 4. Hereinafter, themanufacture of the MCM-1C is explained in conjunction with FIG. 18 toFIG. 23. FIG. 18 to FIG. 23 are cross-sectional views of an essentialpart for explaining the manufacture of the MCM-1C ((a) being across-sectional view taken at a position along a line C-C in FIG. 16,(b) being a cross-sectional view taken at a position along a line C-C inFIG. 16).

[0154] First of all, the printed wiring board 40 for taking pluralpieces shown in FIG. 9 is prepared and, at the same time, thesemiconductor chip (stud-bump connection semiconductor chip) 3 shown inFIG. 6 and the semiconductor chips (solder-bump connection semiconductorchip) 4 shown in FIG. 7 are prepared.

[0155] Next, as shown in FIG. 18, using a dispense method, for example,bonding material 52 in a paste form is supplied onto the connectingportions 22 a arranged on respective chip mounting regions 42 of theplurality of board forming regions 41 formed over one main surface ofthe printed wiring board 40. As the bonding material 52, a solder pastematerial having a melting point which is lower than a melting point ofthe stud bumps 7 of the semiconductor chip 3 and higher than a meltingpoint of the solder bumps 8 of the semiconductor chip 4 is used. As thesolder paste material, a solder paste material which mixes at leastminute solder particles and flux therein is used. In this embodiment,the solder paste material which mixes solder particles of 98 [wt%]Pb(lead)-2 [wt %]Sn(tin) composition having a melting point ofapproximately 300° C., for example, therein is used. The stud bumps 7and the solder bumps 8 of this embodiment are formed of thesubstantially same material as those of the previously-mentionedembodiment 1. The dispense method is a method which projects the solderpaste material from a narrow nozzle and applies the solder pastematerial.

[0156] Next, as shown in FIG. 19, the printed wiring board 40 isarranged on the heat stage 51 and, thereafter, the semiconductor chip 3is conveyed to a position above the chip mounting region 42 such thatthe stud bumps 7 are positioned above the connecting portions 22 a by acollet 53. Then, the printed wiring board 40 is heated by a heat stage51 and the semiconductor chip 3 is heated by the collet 53 so as to meltthe bonding material 52 as shown in FIG. 20. Thereafter, the meltedbonding material 52 is solidified. Accordingly, the semiconductor 3 ismounted on the chip mounting region 42 on one main surface of theprinted wiring board 40. This mounting of the semiconductor chip 3 isperformed for respective chip mounting regions 42 of the plurality ofboard forming regions 40 provided to one main surface of the printedwiring board 40.

[0157] Next, to connecting portions 23 a arranged on respective chipmounting regions 43 of the plurality of board forming regions 41 on onemain surface of the printed wiring board 40, flux is supplied by ascreen printing method, for example. Thereafter, as shown in FIG. 21,the semiconductor chips 4 are arranged on the respective chip mountingregions 43 of the plurality of board forming regions 41 such that thesolder bumps 8 are positioned on the connecting portions 23 a.

[0158] Next, the printed wiring board 40 is conveyed to an infrared rayreflow furnace, for example, so as to melt the solder bumps 8.Thereafter, the melted solder bumps 8 are solidified. Accordingly, asshown in FIG. 22, the semiconductor chips 4 are mounted on therespective chip mounting regions 43 of the plurality of board formingregions 41 formed over one main surface of the printed wiring board 40.

[0159] Here, since the stud bump 7 and the bonding material 52 areformed of a material having a melting point higher than a melting pointof the solder bump 8, the stud bump 7 and the bonding material 52 arenot melted at the time of melting the solder bump 8.

[0160] Further, when the semiconductor 3 and the semiconductor chips 4are collectively mounted, since the stud bumps 7 are smaller than thesolder bumps 8, at the time of conveying the printed wiring board 40 tothe reflow furnace or at the time of performing the reflow, thepositional displacement that the stud bumps 7 are displaced from theconnection portions 22 a is liable to easily occur. However, as in thecase of this embodiment, by mounting the semiconductor 3 using thebonding material 52 made of the material having a melting point higherthan a melting point of the solder bump 8 before conveying the printedwiring board 40 to the reflow furnace and mounting the semiconductorchip 4, at the time of conveying the printed wiring board 40 to thereflow furnace or at the time of performing the reflow, the positionaldisplacement that the stud bumps 7 a are displaced from the connectionportions 22 a does not occur and hence, it is possible to suppress theconnection failure between the connecting portions 22 a of the printedwiring board 40 and the stud bumps 7.

[0161] Next, as shown in FIG. 23, in a gap region defined between thechip mounting region 42 formed over one main surface of the printedwiring board 40 and the semiconductor chip 3 as well as in a gap regiondefined between the chip mounting region 43 formed over one main surfaceof the printed wiring board 40 and the semiconductor chip 4, anunderfill resin 10 is filled.

[0162] Here, when the underfill resin 10 is filled between the printedwiring board 40 and the semiconductor chip 3 after mounting thesemiconductor chip 3 and before mounting the semiconductor chip 4, dueto spreading of wetting of the underfill resin 10, there exists apossibility that the connecting portion 23 a of the chip mounting region43 is covered with the underfill resin 10 and hence, it is necessary towiden the distance between the chip mounting regions 42, 43. However, byfilling the underfill resin 10 after mounting the semiconductor chip 4as in the case of this embodiment, there is no possibility that theconnecting portion 23 a of the chip mounting region 43 is covered due tospreading of wetting of the underfill resin 10 and hence, it is possibleto narrow the distance between the chip mounting regions 42 and 43.

[0163] Further, when the underfill resin 10 is filled in the gap regiondefined between the printed wiring board 40 and the semiconductor chip 3before mounting the semiconductor chip 4 and the underfill resin 10 isfilled in the gap region defined between the printed wiring board 40 andthe semiconductor chip 4 after mounting the semiconductor chip 4, heatgenerated in the step of mounting the semiconductor 4 is applied to theunderfill resin 10 which is already filled. However, as in the case ofthis embodiment, by filling the underfill resin 10 into the gap regiondefined between the chip mounting region 42 formed over one main surfaceof the printed wiring board 40 and the semiconductor chip 3 and into thegap region defined between the chip mounting region 43 formed over onemain surface of the printed wiring board 40 and the semiconductor chip 4after steps of mounting the semiconductor chip 3 and the semiconductorchip 4, it is possible to prevent the heat generated in the step ofmounting the semiconductor chip 3 or the semiconductor 4 from beingapplied to the previously filled underfill resin 10 and hence, it ispossible to prevent the cracks which occur in the underfill resin 10attributed to the rupture of bonding in the resin. Further, by fillingthe underfill resin 10 in the same step, it is possible to simplify thenumber of manufacturing steps.

[0164] Thereafter, by performing the steps substantially equal to thesteps of the above-mentioned embodiment 1, it is possible tosubstantially complete the MCM-1C shown in FIG. 16 and FIG. 17.

[0165] In this manner, according to this embodiment, it is possible toobtain following advantageous effects.

[0166] (1) In the manufacture of the MCM-1C, before conveying theprinted wiring board 40 to the reflow furnace and mounting thesemiconductor chips (solder-bump semiconductor chips) 4, thesemiconductor chip (stud-bump connection semiconductor chip) 3 ismounted using the bonding material 52 made of the material having amelting point higher than a melting point of the solder bump 8.Accordingly, at the time of conveying the printed wiring board 40 to thereflow furnace or at the time of performing the reflow, the positionaldisplacement that the stud bumps 7 are displaced from the connectionportions 22 a does not occur and hence, it is possible to suppress theconnection failure between the connecting portions 22 a of the printedwiring board 40 and the stud bumps 7. As a result, it is possible toenhance a yield rate of the MCM-1C.

[0167] (2) In the manufacture of the MCM-1C, by filling the underfillresin 10 after mounting the semiconductor chips 3 and 4, there is nopossibility that the connecting portion 23 a of the chip mountingregions 42 and 43 is covered due to spreading of wetting of theunderfill resin 10 and hence, it is possible to narrow the distancebetween the chip mounting regions 42 and 43. As a result, the MCM-1C canbe miniaturized.

[0168] (3) In the manufacture of the MCM-1C, by filling the underfillresin 10 into the gap region defined between the chip mounting region 42formed over one main surface of the printed wiring board 40 and thesemiconductor chip 3 and into the gap region defined between the chipmounting region 43 formed over one main surface of the printed wiringboard 40 and the semiconductor chip 4 after the step of mounting thesemiconductor chips 3 and 4, it is possible to prevent the heatgenerated in the step of mounting the semiconductor chip 3 and thesemiconductor 4 from being applied to the underfill resin 10 and hence,it is possible to prevent the cracks which occur in the underfill resin10 attributed to the rupture of bonding in the resin. As a result, it ispossible to suppress the lowering of the mechanical strength of theunderfill resin 10 whereby the rupture of the stud bumps 7 attributed tothe difference in thermal expansion coefficient between thesemiconductor chip 3 and the printed wiring board 2 can be suppressed.Further, by filling the underfill resin 10 in the same step, it ispossible to simplify the number of manufacturing steps.

[0169] Here, although the explanation is made with respect to theexample in which the semiconductor chip 4 is used as an electroniccomponent having the solder bumps in this embodiment, the CSP typesemiconductor device 60 shown in FIG. 15 may be used as the electroniccomponent having the solder bumps.

[0170] Further, although the explanation is made with respect to theexample in which the bonding material 52 in a paste form is supplied tothe connecting portions 22 a using the dispense method in thisembodiment, the MCM may be manufactured by using the printed wiringboard in which bonding material in a solid form is preliminarily formedover the connecting portions 22 a.

EMBODIMENT 4

[0171]FIG. 24 and FIG. 25 are cross-sectional views of an essential partfor explaining the manufacture of an MCM of an embodiment 4 of thepresent invention((a) being a cross-sectional view taken at the sameposition as a line C-C in FIG. 16, (b) being a cross-sectional viewtaken at the same position as a line D-D in FIG. 16). The manufacture ofthe MCM of this embodiment is explained hereinafter in conjunction withFIG. 24 and FIG. 25.

[0172] First of all, the printed wiring board 40 for taking pluralpieces shown in FIG. 9 is prepared and, at the same time, thesemiconductor chip (stud-bump connection semiconductor chip) 3 shown inFIG. 6 and the semiconductor chips (solder-bump connection semiconductorchip) 4 shown in FIG. 7 are prepared.

[0173] Next, as shown in FIG. 24, before mounting the semiconductorchips 4, the semiconductor chips 3 are mounted on respective chipmounting regions of a plurality of board forming regions 41 on one mainsurface of the printed wiring board 40. Mounting of the semiconductorchips 3 is performed in the same manner as the previously-mentionedembodiment 3. However, as the bonding material 52, this embodiment usesa solder paste material in which solder particles of 63 [wt%]Pb(lead)-37 [wt %]Sn(tin) composition having a melting point ofapproximately 183° C., for example, are mixed.

[0174] Next, as shown in FIG. 25, the semiconductor chips 4 are mountedon respective chip mounting regions 43 of a plurality of board formingregions 41 formed over one main surface of the printed wiring board 40.Mounting of the semiconductor chips 4 is performed as follows. A flux issupplied to the connecting portions 23 a by a dispense method, forexample. Thereafter, the semiconductor chips 4 are conveyed onto thechip mounting region 43 by a collet 54 such that the solder bumps 8 arepositioned above the connecting portions 23 a. Thereafter, the printedwiring board 40 is heated using a heat stage 51 and, at the same time,the semiconductor chips 4 are heated by the collet 54 so as to melt thesolder bumps 8. Thereafter, melted solder bumps 8 are solidified.Mounting of the semiconductor chips 4 are performed for respective chipmounting regions 43 of a plurality of board forming regions 41 formedover one main surface of the printed wiring board 40.

[0175] Thereafter, by applying steps substantially equal to those of thepreviously-mentioned embodiment 3, the MCM is almost completed.

[0176] In this embodiment, at the time of mounting the semiconductorchips (stud-bump-mounting semiconductor chips) 3, mounting of thesemiconductor chips 3 is performed in a state that the semiconductorchips are pushed by the collets 53 and hence, even when thesemiconductor chip 3 has electrode pads with a narrow arrangement pitch,it is possible to mount the semiconductor chip 3 without the positionaldisplacement. Further, at the time of mounting the semiconductor chips4, the semiconductor chips 4 are selectively heated by the collet 54such that the temperature of the semiconductor chips 4 is set higherthan the temperature of the semiconductor chips 3 and, at the same time,the temperature of the semiconductor chips 3 is set not higher than amelting point of the bonding material 52. Accordingly, it is possible tomount the semiconductor chips 4 without melting the bonding material 52.As a result, it is possible to enhance a yield rate of the MCM. Further,due to such a method, as the bonding material 52, it is also possible toadopt a material which has a melting point equal to a melting point ofthe solder bumps 8 or lower than a melting point of the solder bumps 8.

[0177] Here, in this embodiment, although the explanation is made withrespect to the example in which the semiconductor chips (stud-bumpconnection semiconductor chip) 3 are mounted prior to mounting of thesemiconductor chips 4 (solder-bump connection semiconductor chips) 4, itis possible to obtain the substantially same advantageous effect bymounting the semiconductor chips 4 prior to mounting of thesemiconductor chips 3.

EMBODIMENT 5

[0178]FIG. 26 and FIG. 27 are cross-sectional views of an essential partfor explaining the manufacture of an MCM of an embodiment 5 of thepresent invention ((a) being a cross-sectional view taken at the sameposition as a line C-C in FIG. 16, (b) being a cross-sectional viewtaken at the same position as a line D-D in FIG. 16). Hereinafter, themanufacture of the MCM of this embodiment is explained in conjunctionwith FIG. 26 and FIG. 27.

[0179] First of all, the printed wiring board 40 for taking pluralpieces shown in FIG. 9 is prepared and, at the same time, thesemiconductor chip (stud-bump connection semiconductor chip) 3 shown inFIG. 6 and the semiconductor chips (solder-bump connection semiconductorchip) 4 shown in FIG. 7 are prepared.

[0180] Next, as shown in FIG. 26, before mounting the semiconductorchips 3, the semiconductor chips 4 are mounted on respective chipmounting regions 43 of a plurality of board forming regions 41 on onemain surface of the printed wiring board 40. Mounting of thesemiconductor chips 4 is performed as follows. A flux is supplied by ascreen printing method, for example, to connecting portions 23 a whichare arranged in respective chip mounting regions 43 of a plurality ofboard forming regions 41 formed over one main surface of the printedwiring board 40. Thereafter, the semiconductor chips 4 are arranged onthe respective chip mounting regions 43 of a plurality of board formingregions 41 such that the solder bumps 8 are positioned on the connectingportions 23 a. Thereafter, the printed wiring board 40 is conveyed to aninfrared ray reflow furnace, for example, to melt the solder bumps 8.Thereafter, the melted solder bumps 8 are solidified.

[0181] Next, the semiconductor chips 3 are mounted on respective chipmounting regions 42 of a plurality of board forming regions 41 formedover one main surface of the printed wiring board 40. Mounting of thesemiconductor chips 4 is performed as follows. First of all, a bondingmaterial 52 in a paste form is supplied by a dispense method, forexample, to the connecting portions 22 a arranged on respective chipmounting regions 42 of the plurality of board forming regions 41 formedover one main surface of the printed wiring board 40. Thereafter, asshown in FIG. 27, the printed wiring board 40 is arranged on a heatstage 51. Then, the semiconductor chips 3 are conveyed onto the chipmounting region 42 by a collet 53 such that the stud bumps 7 arepositioned above the connecting portions 22 a. Thereafter, the printedwiring board 40 is heated using a heat stage 51 and, at the same time,the semiconductor chips 3 are heated by the collet 53 so as to melt thebonding material 52 as shown in FIG. 27. Thereafter, melted bondingmaterial 52 is solidified. Mounting of the semiconductor chips 3 isperformed for respective chip mounting regions 42 of a plurality ofboard forming regions 41.

[0182] Thereafter, by applying steps substantially equal to those of thepreviously-mentioned embodiment 3, the MCM is almost completed.

[0183] In this embodiment, after mounting the semiconductor chips(solder-bump connection semiconductor chips) 4, mounting of thesemiconductor chips 4 is performed in a state that the semiconductorchips 3 are pressed by the collets 53 and hence, even when thesemiconductor chip 3 has electrode pads with a narrow arrangement pitch,it is possible to mount the semiconductor chip 3 without the positionaldisplacement. Further, at the time of mounting the semiconductor chips3,the semiconductor chips 3 are selectively heated by the collet 53 suchthat the temperature of the semiconductor chips 3 is set higher than thetemperature of the semiconductor chips 4. Accordingly, it is possible tomount the semiconductor chips 3 without melting the solder bumps 8. As aresult, it is possible to enhance a yield rate of the MCM.

[0184] Further, to the connecting portions 23 a which have a large pitchcompared to a pitch of the connecting portions 22 a, the flux or thesolder paste can be supplied by a screen printing method. Then, bycollectively performing the supply of flux to a plurality of connectingportions 23 a by a screen printing method, compared to a case in whichthe flux is supplied to every connecting portion 23 a by a dispensemethod, it is possible to shorten the step. Further, by performing thestep of supplying flux using the screen printing before mounting thesemiconductor chips 3, it is possible to narrow the distance between thechip mounting region 42 and the chip mounting region 43 in the inside ofthe respective board forming regions 41. As a result, the MCM can beminiaturized.

[0185] Although the inventions made by the inventors have beenspecifically explained based on the above-mentioned embodiments, it isneedless to say that the present inventions are not limited to theabove-mentioned embodiments and various modifications can be made withina range without departing from the gist of the present inventions.

[0186] To briefly explain the advantageous effects obtained by typicalinventions among the inventions disclosed by the present application,they are as follows.

[0187] According to the present invention, it is possible to enhance thereliability of the electronic device.

[0188] According to the present invention, it is possible to enhance themanufacturing yield rate of the electronic device.

[0189] Industrial Applicability

[0190] As has been explained heretofore, the electronic device accordingto the present invention is advantageously used as the electronic devicewhich mounts electronic components which differ in types of projectionelectrodes on the same board in a mixed form and, more particularly, theelectronic device according to the present invention is advantageouslyused as the MCM which mounts the solder-bump connection chips and thestud-bump connection chips on the same board in a mixed form.

1. A manufacturing method of an electronic device comprising the stepsof: preparing a printed wiring board having a first region and a secondregion which differ from each other over one main surface thereof, afirst electronic component having a plurality of first projectionelectrodes over one main surface thereof, and a second electroniccomponent having a plurality of second projection electrodes which havea melting point higher than a melting point of the first projectionelectrodes over one main surface thereof; mounting the first electroniccomponent to the first region of one main surface of the printed wiringboard by melting the plurality of first projection electrodes; andmounting the second electronic component to the second region of onemain surface of the printed wiring board by compression-bonding thesecond electronic component while heating in a state that an adhesiveresin is interposed between the second region of one main surface of theprinted wiring board and one main surface of the second electroniccomponent, wherein the step of mounting the second electronic componentis performed after the step of mounting the first electronic component.2. A manufacturing method of an electronic device according to claim 1,wherein the adhesive resin is a thermosetting insulation resin.
 3. Amanufacturing method of an electronic device according to claim 2,wherein the thermosetting insulation resin is an epoxy-based resin.
 4. Amanufacturing method of an electronic device according to claim 2,wherein the thermosetting insulation resin is a sheet-like or apaste-like resin.
 5. A manufacturing method of an electronic deviceaccording to claim 1, wherein the adhesive resin is an anisotropicconductive resin which is produced by mixing a large number ofconductive particles in the inside of a thermosetting insulation resin.6. A manufacturing method of an electronic device according to claim 5,wherein the thermosetting insulation resin is an epoxy-based resin.
 7. Amanufacturing method of an electronic device according to claim 5,wherein the anisotropic conductive resin is a sheet-like or a paste-likeresin.
 8. A manufacturing method of an electronic device according toclaim 1, wherein the first projection electrodes are solder bumps, andwherein the second projection electrodes are stud bumps.
 9. Amanufacturing method of an electronic device according to claim 1,wherein an arrangement pitch of the plurality of second projectionelectrodes is smaller than an arrangement pitch of the plurality offirst projection electrodes.
 10. A manufacturing method of an electronicdevice according to claim 1, wherein the first and the second electroniccomponents are formed of a semiconductor chip in which a circuit isincorporated.
 11. A manufacturing method of an electronic deviceaccording to claim 1, wherein the first electronic component is formedof a semiconductor chip which includes: a semiconductor substrate; aplurality of semiconductor elements which are formed over one mainsurface of the semiconductor substrate; a plurality of first electrodepads which are formed over one main surface of the semiconductorsubstrate; a plurality of second electrode pads which are formed as alayer above the plurality of first electrode pads and are respectivelyelectrically connected to the plurality of first electrode pads, theplurality of second electrode pads being arranged at an arrangementpitch wider than an arrangement pitch of the plurality of firstelectrode pads; and the plurality of first projection electrodes whichare respectively connected to the plurality of second electrode pads,and wherein the second electronic component is formed of a semiconductorchip which includes a semiconductor substrate, a plurality ofsemiconductor elements which are formed over one main surface of thesemiconductor substrate, a plurality of electrode pads which are formedover one main surface of the semiconductor substrate, and the pluralityof second projection electrodes which are respectively connected to theplurality of electrode pads. 12-25 (Cancelled)
 26. A manufacturingmethod of an electronic device comprising the steps of: (a) preparing aprinted wiring board having a first region and a second region whichdiffer from each other over one main surface thereof, wherein aplurality of first connecting portions are arranged in the first regionand a plurality of second connecting portions are arranged in the secondregion, a first electronic component having a plurality of firstprojection electrodes over one main surface thereof, and a secondelectronic component having a plurality of second projection electrodeswhich have a melting point higher than a melting point of the firstprojection electrodes over one main surface thereof; (b) electricallyconnecting the plurality of second connecting portions and the pluralityof second projection electrodes to each other by melting a bondingmaterial having a melting point higher than a melting point of the firstprojection electrodes and lower than a melting point of the secondprojection electrodes; and (c) electrically connecting the plurality offirst connecting portions and the plurality of first projectionelectrodes by melting the plurality of first projection electrodes,wherein the step (b) is performed before the step (c).
 27. Amanufacturing method of an electronic device according to claim 26,wherein the plurality of first projection electrodes are solder bumps,and wherein the plurality of second projection electrodes are studbumps.
 28. A manufacturing method of an electronic device according toclaim 26, wherein an arrangement pitch of the plurality of secondprojection electrodes is smaller than an arrangement pitch of theplurality of first projection electrodes.
 29. A manufacturing method ofan electronic device according to claim 26, wherein the first and thesecond electronic components are formed of a semiconductor chip in whicha circuit is incorporated.
 30. A manufacturing method of an electronicdevice according to claim 26, wherein the first electronic component isformed of a semiconductor chip which includes: a semiconductorsubstrate; a plurality of semiconductor elements which are formed overone main surface of the semiconductor substrate; a plurality of firstelectrode pads which are formed over one main surface of thesemiconductor substrate; a plurality of second electrode pads which areformed as a layer above the plurality of first electrode pads and arerespectively electrically connected to the plurality of first electrodepads, the plurality of second electrode pads being arranged at anarrangement pitch wider than an arrangement pitch of the plurality offirst electrode pads; and the plurality of first projection electrodeswhich are respectively connected to the plurality of the secondelectrode pads, and wherein the second electronic component is formed ofa semiconductor chip which includes a semiconductor substrate, aplurality of semiconductor elements which are formed over one mainsurface of the semiconductor substrate, a plurality of electrode padswhich are formed over one main surface of the semiconductor substrate,and the plurality of second projection electrodes which are respectivelyconnected to the plurality of electrode pads.
 31. A manufacturing methodof an electronic device according to claim 26, wherein the firstelectronic component is a semiconductor device which packages asemiconductor chip incorporating a circuit therein, and wherein thesecond electronic component is a semiconductor chip incorporating acircuit therein.
 32. A manufacturing method of an electronic deviceaccording to claim 26, wherein the first electronic component is asemiconductor device which includes a printed wiring board, asemiconductor chip being arranged over one main surface side of theprinted wiring board and incorporating a circuit therein, and theplurality of first projection electrodes which are arranged over anothermain surface side facing one main surface of the printed~wiring board inan opposed manner, and wherein the second electronic component is asemiconductor chip incorporating a circuit therein.
 33. A manufacturingmethod of an electronic device according to claim 26, further including,after the step (b), a step of: filling an underfill resin between thefirst region formed over one main surface of the printed wiring boardand the first electronic component as well as between the second regionformed over one main surface of the printed wiring board and the secondelectronic component. 34-40 (Cancelled)
 41. A manufacturing method of anelectronic device comprising the steps of: (a) preparing a printedwiring board having a first region and a second region which differ fromeach other over one main surface thereof, wherein a plurality of firstconnecting portions are arranged over the first region and a pluralityof second connecting portions are arranged over the second region, afirst electronic component having a plurality of first projectionelectrodes over one main surface thereof, and a second electroniccomponent having a plurality of second projection electrodes which havea melting point higher than a melting point of the first projectionelectrodes over one main surface thereof; (b) electrically connectingthe plurality of first connecting portions and the plurality of firstprojection electrodes by melting the plurality of first projectionelectrodes, and (c) after the step (b), electrically connecting theplurality of second connecting portions and the plurality of secondprojection electrodes to each other by melting a bonding material havinga melting point lower than a melting point of the second projectionelectrodes.
 42. A manufacturing method of an electronic device accordingto claim 41, wherein the plurality of first projection electrodes aresolder bumps, and wherein the plurality of second projection electrodesare stud bumps.
 43. A manufacturing method of an electronic deviceaccording to claim 41, wherein an arrangement pitch of the plurality ofsecond projection electrodes is smaller than an arrangement pitch of theplurality of first projection electrodes.
 44. A manufacturing method ofan electronic device according to claim 41, wherein the first and thesecond electronic components are formed of a semiconductor chip in whicha circuit is incorporated.
 45. A manufacturing method of an electronicdevice according to claim 41, wherein the first electronic component isformed of a semiconductor chip which includes: a semiconductorsubstrate; a plurality of semiconductor elements which are formed overone main surface of the semiconductor substrate; a plurality of firstelectrode pads which are formed over one main surface of thesemiconductor substrate; a plurality of second electrode pads which areformed as a layer above the plurality of first electrode pads and arerespectively electrically connected to the plurality of first electrodepads, the plurality of second electrode pads being arranged at anarrangement pitch wider than an arrangement pitch of the plurality offirst electrode pads; and the plurality of first projection electrodeswhich are respectively connected to the plurality of the secondelectrode pads, and wherein the second electronic component is formed ofa semiconductor chip which includes a semiconductor substrate, aplurality of semiconductor elements which are formed over one mainsurface of the semiconductor substrate, a plurality of electrode padswhich are formed over one main surface of the semiconductor substrate,and the plurality of second projection electrodes which are respectivelyconnected to the plurality of electrode pads.
 46. A manufacturing methodof an electronic device according to claim 41, wherein the firstelectronic component is a semiconductor device which packages asemiconductor chip incorporating a circuit therein, and wherein thesecond electronic component is a semiconductor chip incorporating acircuit therein.
 47. A manufacturing method of an electronic deviceaccording to claim 41, wherein the first electronic component is asemiconductor device which includes a printed wiring board, asemiconductor chip being arranged over one main surface side of theprinted wiring board and incorporating a circuit therein, and theplurality of first projection electrodes which are arranged over anothermain surface side facing one main surface of the printed wiring board inan opposed manner, and wherein the second electronic component is asemiconductor chip incorporating a circuit therein.
 48. A manufacturingmethod of an electronic device according to claim 41, further including,after the step (c), a step of filling an underfill resin between thefirst region formed over one main surface of the printed wiring boardand the first electronic component.
 49. A manufacturing method of anelectronic device according to claim 41, further including, after thestep (c), a step of filling an underfill resin between the first regionformed over one main surface of the printed wiring board and the firstelectronic component as well as between the second region formed overone main surface of the printed wiring board and the second electroniccomponent.
 50. A manufacturing method of an electronic device comprisingthe steps of: (a) preparing a printed wiring board having a first regionand a second region which differ from each other, wherein a plurality offirst connecting portions are arranged over the first region and aplurality of second connecting portions are arranged over the secondregion, a first electronic component having a plurality of firstprojection electrodes over one main surface thereof, and a secondelectronic component having a plurality of second projection electrodesover one main surface thereof; (b) electrically connecting the pluralityof second connecting portions and the plurality of second projectionelectrodes by melting a bonding material having a melting point lowerthan a melting point of the second projection electrodes; and (c) afterthe second step, electrically connecting the plurality of firstconnecting portions and the plurality of first projection electrodes toeach other by melting the plurality of first projection electrodes,wherein the step (c) is performed by heating the first electroniccomponent such that a temperature of the first electronic componentbecomes higher than a temperature of the second electronic component.51. A manufacturing method of an electronic device according to claim50, wherein the plurality of first projection electrodes are solderbumps, and wherein the plurality of second projection electrodes arestud bumps.
 52. A manufacturing method of an electronic device accordingto claim 50, wherein an arrangement pitch of the plurality of secondprojection electrodes is smaller than an arrangement pitch of theplurality of first projection electrodes.
 53. A manufacturing method ofan electronic device according to claim 50, wherein the first and thesecond electronic components are formed of a semiconductor chip in whicha circuit is incorporated.
 54. A manufacturing method of an electronicdevice according to claim 50, wherein the first electronic component isformed of a semiconductor chip which includes: a semiconductorsubstrate; a plurality of semiconductor elements which are formed overone main surface of the semiconductor substrate; a plurality of firstelectrode pads which are formed over one main surface of thesemiconductor substrate; a plurality of second electrode pads which areformed as a layer above the plurality of first electrode pads and arerespectively electrically connected to the plurality of first electrodepads, the plurality of second electrode pads being arranged at anarrangement pitch wider than an arrangement pitch of the plurality offirst electrode pads; and the plurality of first projection electrodeswhich are respectively connected to the plurality of the secondelectrode pads, and wherein the second electronic component is formed ofa semiconductor chip which includes a semiconductor substrate, aplurality of semiconductor elements which are formed over one mainsurface of the semiconductor substrate, a plurality of electrode padswhich are formed over one main surface of the semiconductor substrate,and the plurality of second projection electrodes which are respectivelyconnected to the plurality of electrode pads.
 55. A manufacturing methodof an electronic device according to claim 50, wherein the firstelectronic component is a semiconductor device which packages asemiconductor chip incorporating a circuit therein, and wherein thesecond electronic component is a semiconductor chip incorporating acircuit therein.
 56. A manufacturing method of an electronic deviceaccording to claim 50, wherein the first electronic component is asemiconductor device which includes a printed wiring board, asemiconductor chip being arranged over one main surface side of theprinted wiring board and incorporating a circuit therein, and theplurality of first projection electrodes which are arranged over anothermain surface side facing one main surface of the printed wiring board inan opposed manner, and wherein the second electronic component is asemiconductor chip incorporating a circuit therein.
 57. A manufacturingmethod of an electronic device according to claim 50, further including,after the step (c), a step of filling an underfill resin between thefirst region formed over one main surface of the printed wiring boardand the first electronic component.
 58. A manufacturing method of anelectronic device according to claim 50, further including, after thestep (c), a step of filling an underfill resin between the first regionformed over one main surface of the printed wiring board and the firstelectronic component as well as between the second region formed overone main surface of the printed wiring board and the second electroniccomponent.